1. Field of the Invention
The present invention relates to a microcomputer, and more particularly to that including therein a display controller for displaying characters and symbols, etc., on a display unit using a cathode-ray tube and the like in a raster scan system.
2. Description of the Prior Art
FIG. 4 is a block diagram illustrating a basic arrangement of a prior microcomputer including therein a display controller.
As shown in the figure, a CPU 1 of the microcomputer controls input/output of encoded character data into/out of a display refresh memory 9.
A basic controller 3 has a pointer (not shown) indicative of a line now in display, and issues an address signal for accessing the display refresh memory 9 in synchronism with a timing signal in need of display control and in synchronism with horizontal and vertical sync. signals HD and VD of raster scanning in a display unit (not shown).
Designated at 9 is the display refresh memory, in which codes of characters and symbols are respectively stored at one address per character. Designated at 5 is a character pattern generator circuit, that reads a pattern memory (not shown) in which a dot pattern comprising characters and symbols is stored, with use of codes of those characters and symbols as address, and that generates a character dot pattern.
Likewise, designated ht 4 is an address controller which issues an address signal to thereby read a character code from the display refresh memory 9, the character code serving as an address in the pattern memory of the character pattern generator circuit 5 to permit a dot pattern of that character to be generated.
Designated at 6 is an output controller (display controller), which issues the character dot pattern so read from the character pattern generator circuit 5 in the form of a bit serial video signal displayed by a raster scan system in accordance with a timing signal from the basic controller 3.
FIG. 5 is a block diagram illustrating a prior arrangement of the address controller 4 of FIG. 4. As shown in the figure, designated at 7 is an address counter, and 8 is a coincidence circuit. Likewise, designated at A is a constant, B is a clear signal for the address counter 7, C is an incremental signal for the same, D is a display line pointer signal in the basic controller 3 for determining high order bits of an address signal, and E is an 1-scan-display end signal.
FIG. 6 illustrates an exemplary display yielded by the control of the address controller of FIG. 5 which demonstrates a character in a matrix form of 4 lines.times.8 rows.
FIG. 7 illustrates addresses in the display refresh memory 9 employed correspondingly to the display of FIG. 6.
In succession, the circuit of FIG. 5 will be described with reference to FIGS. 4 to 7. Prior to operation of any display, codes of characters(in the present example, 32 characters of "0" to "9" and "A" to "V") displayed on a screen are all stored in the display refresh memory 9 at corresponding addresses (in this example, "0" to "37") with the aid of the CPU 1. First, the address counter 7 is cleared to "0" by a signal B from the basic controller 3, which has detected a display position on a 1st line to provide "0" to the low order of an address signal and "0" of a value of a display line pointer indicative of the first line to the high order of a character "0" of the same, and thus a code of a character "0" at an address "00" in the display refresh memory 9, i.e., at the first line and first row is read. Contents in the address counter 7 are incremented by a numerical value "1" at a timeby the signal C for each character to change to "00", "01", "02",... ( in decimal rotation. the same shall apply hereinafter.).
While, the constant A, which determines an end address, is "7" in this example, and hence a coincidence circuit 8 provides the 1-scan-display end signal E from the address counter 7 to the basic controller 3 when the low order address signal changes to "7". The contents in the address counter 7 are cleared by the signal B to return to "0". With this situation repeated by the number of raster scan lines which constitute one line, the display on the 1st line is finished. The signal D remains unchanged for that time, i.e., "0". In succession, when the basic controller 3 detects a display position on the 2nd line, the address counter 7 is again cleared by the signal B to "0", and a character code of a character 8 stored at an adress 10 is read from the display refresh memory 9, since the signal D has changed to "1", a value of a line display pointer on the second line. In addition, the address counter 7 is incremented by the signal C for each character. When the address signal from the address counter 7 changes to "7", a value of the constant A, the coincidence circuit 8 provides the 1-scan-end signal E. With this situation repeated by the number of raster scan lines, which constitute one line, the display on the second line is finished. With this operation repeated for the third line, fourth line and so on in succession, a display over one screen is achieved.
Accordingly, when a character or a pattern of 4 lines.times.8 rows is displayed with the prior arrangement, 32 display refresh memories are required.